Basic architecture

The Logic74 is a homebrew micro(macro)controller which is completely built from 74lsxxx logic gates.

Although I decided about the general architecture mostly without any commercial design in my mind, I figured out, that it fits to the AVR architecture in many points. That's why I implemented the most important instructions based on the AVR instructions set.

Key Features:

- 8-bit CPU

- 16-bit program counter

- 65kx8-bit program memory

- 256x8-bit RAM

- 256x8-bit I/O

- 50 kHz clock frequency (much faster should be possible but not testet yet)

- 8-bit Stack Pointer

- 4 Registers (up to 256 possible)

- 4 external Interrupts (one interrupt vector to program address 0x0003)

The architecture is based on a Harward design. The address space between program data and RAM-/IO-data is separated from each other.

The program address space is 16-bit wide, which means you can address 65k of program addresses.

The data space is 8-bit wide and can be used to address both RAM-data and IO-data, which leads to 256 RAM-addresses and 256 I/O-addresses. RAM-data can be addressed via LDS and STS instructions, I/O-data can be addressed via IN and OUT instructions.

The common data bus is 8-bit wide.

To keep things simple and easy to design, I decided to implement the control unit as microcode in dedicated Control-Unit-ROMs which lead to a classical CISC architecture.

For the 8-bit ALU, I took 2x 74LS181N ICs which are dedicated 4-BIT ARITHMETIC LOGIC UNIT chips.

LOGIC74 Memory map

Instruction set

The instruction set is based on the AVR instruction set and includes 38 instructions which looked the most important to me.

Every instruction uses 3 bytes in the program memory:

1. byte: opcode of the instruction

2. byte: first argument (could be a Register, an immediate value, 8-bit RAM/IO-address, high byte of an 16bit program ROM address)

3. byte: second argument (could be a Register, an immediate value, 8-bit RAM/IO-address, low byte of an 16-bit program ROM address)

If the 2nd or 3rd byte is not used by the instruction, it has to be filled with 0x00 or any other value you want.

LOGIC74 Instruction set summary

Block diagram

Based on the basic architecture and instruction set, the block diagram includes all the modules and data paths, which are needed, for executing the instructions.

On the top level of the block diagram, the CPU is shown as one block. The program data is stored in the Program-ROM which is organized as 8-databits with 16-bit address bus.

The RAM- and I/O-data bus is also 8 bit wide with an 8-bit address bus. The LDS and STS instruction uses the /MEMRQ control signal to store and load the data in the RAM-address space, the IN and OUT instruction uses the /IOREQ control signal to load and store the data in the I/O-address space.

LOGIC74 Block diagram top level (download high resolution)

The block diagram of the CPU show all the modules and datapaths, which are needed to execute the instructions. The control unit executes the instruction cycle and sets the control signals for the modules depending on the current instruction and Status-Flags from the Status Register.

LOGIC74 Block diagram CPU level (download high resolution)

Instruction cycle

The instruction cycle is the main loop for executing one instruction after another. In general, it is the same for every instruction. Depending on the instruction, the amount of clock cycles for setting the needed data path and reading/storing the data can be different. This is handled by the microcode sequencer in the control unit.

To keep it simple as possible, every instruction has the same lengths of 3 bytes. This means, that every instruction needs 3 address in the Program-ROM. An example for an instruction cycle (blue) from reset state:

LDI R0,0xAA (Load immediate value 0xAA into Register 0)

reset state: /ROM_OE is set to "low", opcode for LDI at ROM-address 0x0000 is on the databus

clock 1: first Opcode at ROM-address 0x0000 is stored in the instruction register,

clock 2: program counter + 1

clock 3: first argument at ROM-address 0x0001 (0x00 for R0) is stored in the instruction register.

clock 4: program counter + 1

clock 5: second argument at ROM-address 0x0002 (0xAA) is stored in the instruction register

clock 6: second argument from instrucion register is set to ALU input B via MUX, ALU control signals are set to pass thru the data from input B to the databus

clock 7: the data from data bus is stored into the register which is set by the first argument (0x00 for R0)

clock 8: program counter + 1

clock 9: next Opcode at ROM-address 0x0003 is stored in the instruction register

clock 10: program counter + 1

clock 11: ....

Logisim implementation

The whole LOGIC74 microcontroller was modelled and simulated in Logisim. Only with this simulation, it was possible to test all instructions and find failures in the design and the microcode.

LOGIC74 Logisim implementation (download high resolution)

If you want to download the Logisim implementation with a running light test program, you can download it here.

(Simulation speed: 4,1kHz, running light on I/O module with address 0x00, other one set to address 0x01, set one input-bit to 1 to change the running direction)

Microcode

The microcode for all instructions were written in Microsoft Excel. It was probably the most inefficient and error-prone way. :-)

The columns for the Logisim-ROM can be directly copied into the Logisim-ROM which can be found in the control unit sub circuit. For programming the "Hardware"-ROMs, the dedicated columns needs to be copied into a text file and programmed into the ROMs with my self designed ROM-Programmer.

LOGIC74 Microcode start addresses of instructions in Microcode-ROM

LOGIC74 Microcode Generator (e.g. control sequence of the LDI instruction)

If you want to get the Excel document, please feel free to ask me via mail to get the latest version.

Assembler

Although it would be possible to write small assembly test programs and translate them into machine language by hand, I decided to write a small VBA based assembler in Microsoft Excel. The output data is automatically stored in text-files for both Logisim and the "Hardware"-ROMs.

LOGIC74 Assembler

If you want to get the Excel document, please feel free to ask me via mail to get the latest version.

Backplane, schematics and soldering the PCBs

Building the hardware was the most time consuming part. I decided to cluster the modules in a meaningful way and connect them with a back plane.

With an Excel sheet, I tried to stack the PCBs in such a way, that the back plane fits to 3x39 pins for an 100x160mm Eurocard PCB.

LOGIC74 optimizing the PCB sack

LOGIC74 Back plane signals

After that, I created the schematics. Here you can download them:

PROGR_ROM_AB_DB_PUFFER.pdf

CONTROL_UNIT.pdf

INSTRUCTION_REGISTER.pdf

The connections was made with solderable enamelled copper wire. This is the fastest, easiest and most space saving way.

LOGIC74 Program-ROM, CLK and RST soldered on PCB

LOGIC74 Instruction Register soldered on PCB

Putting it all together

After all modules were built up and tested separately, I stacked the PCBs one after another and tested the proper function of all instructions with small test programs and test circuits.

LOGIC74 First stack of Program-ROM, Control Unit and Instruction Register - first instruction cycle tests done

LOGIC74 finished with RAM and I/O-Card running a test program

For further debugging, I needed something to visualize the state of the whole system at once. That was the birth of the LOGIC74 front panel where all available registers and busses are visible with the help of 146 LEDs.

LOGIC74 Front Panel finished soldering and connected

I mounted all together on a wooden plate. Here you can see the final hardware setup running a test program.

LOGIC74 hardware setup finished and tested

Join the ring?

To join the Homebuilt CPUs ring, drop Warren a line, mentioning your page's URL. He'll then add it to the list.
You will need to copy this code fragment into your page.
Note: The ring is chartered for projects that include a home-built CPU. It can emulate a commercial part, that′s OK. But actually using that commercial CPU doesn′t rate. Likewise, the project must have been at least partially built: pure paper designs don′t rate either. It can be built using any technology you like, from relays to FPGAs.